Read Online or Download ACM-SIGDA Physical Design Workshop #4 1993: Layout Synthesis for the New Generation of VLSI ASIC Technologies (Workshop Proceedings) PDF
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Extra info for ACM-SIGDA Physical Design Workshop #4 1993: Layout Synthesis for the New Generation of VLSI ASIC Technologies (Workshop Proceedings)
Figure 10(a) and (b) show the Pruned-raphsof figure 9(c) and their merged versions when the Current-orderis 2 and 3 respectively. Form tree So far, the bipartite graph has been transferred into a loop free directed graph whose vertex indicates a group or a group set. 2) 4 3 ° Pi dh (0ouuu-ada-2) The algorithm is composed of several sub-procedures. Following is their brief descriptions: . 2 (Oz-SR 4 (b) Figure 10: Illustration of vertices merging Theorem 3 The SRT which covers all the vertices exists an a merged directed graph when and only when the graph is connected and there is at most one vertex whose number of incoming edges is zero.
The simulation result points out that tree 2 electrically performs better than that-of tree 1 in terms of both signal delay and waveforms as shown in Figure 3. This example shows the dependence of the interconnector's topology on the 33 ft w'-8 6 4, tree 2 tree ee The load devices at the output terminals are modeled by capacitors. (CMOS technology). Figure 2: Two different trees to implement the same net. adopted circuit model. In general a more accurate circuit model will lead to a better layout design.
Each edge ei in T(n) has an associated edge cost, dij, equal to tie Manhattan distance between its two endpoints ni and nj; the cost of T(n) is the sum of its edge costs. We use t(n,) to denote the signal propagation delay from the source to pin ni. ' The specific routing tree that solves the ORT problem will depend on the method used to estimate delay. Ideally, we would like to compute and optimize delay according to the complete physical attributes of the circuit. To this end, the circuit simulator SPICE is generally regarded as the best available tool for obtaining precise estimates of interconnect delay.